background/intro
deep learning technologies have been widely exploited in Electronic Design Automation (EDA) to assist circuit design
we propose a novel way to integrate the multiple information sources under a unified heterogeneous graph named Circuit Graph, where topological and geometrical information is well integrated.
理解：提出的是一种崭新的表示方法，类似NLP里的Word2Vec 这种吗
EDA里有不同的抽象层次，需要一种抽象表示更好表达异构信息
encounter diverse information sources from various design stages，aka不同的阶段&抽象层次，有不同的信息源
logic synthesis and placement & routing determine the quality and consume the majority of design pipeline time
两类信息：geometrical information and topological information
netlists only contain the topological information
some geometrical information (e.g. positions of standard cells) is available after placement stage.
进而有两种求解路径
geometrical information ⇒ CV
topological information ⇒ GNN
各自都有缺陷
topological information : cannot effectively perceive geometrical structure introduced after 【the placement stage】
geometrical information：cannot handle circuits 【in stages earlier than global placement】 where geometry is not available
!Versatile Multi-stage Graph Neural Network forCircuit Representation(NetlistGNN) 2024-11-19.excalidraw
我们的目的：data structure to represent the circuit, which is adaptive to circuits in both logic synthesis and placement stages ;circuit representation model which is compatible with two stages and various downstream tasks
怎么办
convert the circuit design to Circuit Graph, a heterogeneous graph which preserves most of the topological and geometrical information
two types of vertices i.e. cells and nets
edge: pins(aka,topo-edges) and geom-edges(geometrically close)
design Circuit GNN
conduct message-passing on topo-edges and geom-edges individually
compatible with Circuit Graphs converted from circuits in logic synthesis stage
略
Circuit Graph
Circuit Featurization
netlist composed of cells V and nets U
特征矩阵
X v X u
pins P ⊆ V × U ： bipartite topology between cells V and nets U
the feature matrix of P, preserves their 【interaction details】 交互细节
After placement, the positions of cells px, py are obtained
grid feature 对应 geometrical information，用grid块划分电路，然后分块表示，数学模型计作$$
树 木 特 征 维 度 w h e r e − C x , C y a r e t h e c o l u m n a n d r o w n u m b e r s o f g r i d s ⇒ g r i d 树 木 − D g r i s t h e d i m e n s i o n o f g r i d s ′ r a w f e a t u r e s . g r i d 特 征 维 度 T o p o l o g y f e a t u r e : c e l l s V + n e t s U + p i n s P {V,U,P,X_{u},X_{p},X_{v}}
You can't use 'macro parameter character #' in math mode ### Definition of Circuit Graph /image-20241120000540432.png) 对两个信息统一编码 ### Definition of Circuit Graph /image-20241120000540432.png) 对两个信息统一编码 G= {V,U,\varepsilon_{t},\varepsilon_{G} ,X_{u},X_{v},X_{\varepsilon_{t}},X_{\varepsilon_{G}}}
You can't use 'macro parameter character #' in math mode - we first take pins as topo-edges $\varepsilon_{T}$ ：figb，字面义，接线做节点的直观操作 - Then we link the geometrically-close cells with geom-edges $\varepsilon_{G}$ :figc 链接出现在同一片区的cell 最终终极表示如右上角所示 ## Circuit GNN /image-20241120003405884.png) 1. 特征表示，通过MLP变成hidden state， 2. 图中部，L layers of circuit message-passing，获得deeper representations 3. 右侧：task-adaptive readout layers ## 实验 ### 数据 拥塞预测是在详细布线阶段布线之前预测布线拥塞的任务。它广泛应用于布局工具中，以快速反馈布局质量并避免可布线性差的布局解决方案。为了更早地识别和解决潜在的拥塞结构，多项研究试图在逻辑综合阶段（单元放置之前）预测单元级拥塞。我们在ISPD2011上进行了实验，它总共包含12个VLSI设计。我们使用10个设计（1/2/3/5/6/7/9/11/14/16）进行训练，使用设计#18进行验证，使用设计#19进行测试。我们使用DREAMPlace放置单元并初始化单元、网络和网格的原始特征。NCTU-GR 2.0是一种流行的全局路由器，用于生成网格上的拥塞目标。每个单元的拥塞目标设置为其所在网格的值。对于逻辑综合阶段的拥塞预测，我们仅使用电路的拓扑结构和几何不敏感特征。对于布局中的预测，我们还使用 DREAMPlace 生成的单元位置。 >我有一个问题，ISPD2011看起来只有八个，为啥论文里说有12个 ### 结果  我们首先在逻辑综合阶段评估电路的拥塞预测结果（当几何信息不可用时）（表 1） We first evaluate the congestion prediction result on circuits in logic synthesis stage when geometric information is not available (Tab.1). Then we perform the same task in placement stage as shown in Tab.2 and Appendix Tab.12. Note that geometrical methods pix2pix and LHNN are not aware of cells in circuit design, so they are not evaluated on Cell-level. GAT (w. geom.) is regular GAT with cell positions as additional features. The results show that: (1) In logic synthesis stage, our method with only topo-edges achieves the best performance (16.7% over cutting-edge CongestionNet) with a similar time cost compared to traditional GNN models (5x faster than MPNN which has a time-expensive and underused edge function for netlist input). (2) In placement stage, our method beats the cutting-edge LHNN in most metrics (5.6% on average) while taking only one-tenth of the run-time. The superior performance of our model is primarily attributed to the fusion of both topological and geometrical information. Fig.5 visualizes the predicted congestion values using different methods. Compared to vision-based method [9] and lattice network-based method [15], our proposed method can generate finer congestion prediction with better discriminability. 相关的数据 - we first take pins as topo-edges $\varepsilon_{T}$ ：figb，字面义，接线做节点的直观操作 - Then we link the geometrically-close cells with geom-edges $\varepsilon_{G}$ :figc 链接出现在同一片区的cell 最终终极表示如右上角所示 ## Circuit GNN /image-20241120003405884.png) 1. 特征表示，通过MLP变成hidden state， 2. 图中部，L layers of circuit message-passing，获得deeper representations 3. 右侧：task-adaptive readout layers ## 实验 ### 数据 拥塞预测是在详细布线阶段布线之前预测布线拥塞的任务。它广泛应用于布局工具中，以快速反馈布局质量并避免可布线性差的布局解决方案。为了更早地识别和解决潜在的拥塞结构，多项研究试图在逻辑综合阶段（单元放置之前）预测单元级拥塞。我们在ISPD2011上进行了实验，它总共包含12个VLSI设计。我们使用10个设计（1/2/3/5/6/7/9/11/14/16）进行训练，使用设计#18进行验证，使用设计#19进行测试。我们使用DREAMPlace放置单元并初始化单元、网络和网格的原始特征。NCTU-GR 2.0是一种流行的全局路由器，用于生成网格上的拥塞目标。每个单元的拥塞目标设置为其所在网格的值。对于逻辑综合阶段的拥塞预测，我们仅使用电路的拓扑结构和几何不敏感特征。对于布局中的预测，我们还使用 DREAMPlace 生成的单元位置。 >我有一个问题，ISPD2011看起来只有八个，为啥论文里说有12个 ### 结果  我们首先在逻辑综合阶段评估电路的拥塞预测结果（当几何信息不可用时）（表 1） We first evaluate the congestion prediction result on circuits in logic synthesis stage when geometric information is not available (Tab.1). Then we perform the same task in placement stage as shown in Tab.2 and Appendix Tab.12. Note that geometrical methods pix2pix and LHNN are not aware of cells in circuit design, so they are not evaluated on Cell-level. GAT (w. geom.) is regular GAT with cell positions as additional features. The results show that: (1) In logic synthesis stage, our method with only topo-edges achieves the best performance (16.7% over cutting-edge CongestionNet) with a similar time cost compared to traditional GNN models (5x faster than MPNN which has a time-expensive and underused edge function for netlist input). (2) In placement stage, our method beats the cutting-edge LHNN in most metrics (5.6% on average) while taking only one-tenth of the run-time. The superior performance of our model is primarily attributed to the fusion of both topological and geometrical information. Fig.5 visualizes the predicted congestion values using different methods. Compared to vision-based method [9] and lattice network-based method [15], our proposed method can generate finer congestion prediction with better discriminability. 相关的数据